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mc145442 1
the mc145442 and mc145443 silicongate cmos singlechip lowspeed modems contain a complete frequency shift keying (fsk) modulator, demodu- lator, and filter . these devices are with ccitt v .21 (mc145442) and bell 103 (mc145443) specifications. both devices provide fullduplex or halfduplex 300baud data communication over a pair of telephone lines. they also include a carrier detect circuit for the demodulator section and a duplexer circuit for direct operation on a telephone line through a simple transformer . ? mc145442 compatible with ccitt v.21 ? mc145443 compatible with bell 103 ? lowband and highband bandpass filters onchip ? simplex, halfduplex, and fullduplex operation ? originate and answer mode ? analog loopback configuration for self test ? hybrid network function onchip ? carrier detect circuit onchip ? adjustable transmit level and cd delay timing ? onchip crystal oscillator (3.579 mhz) ? single + 5 v power supply operation ? internal midsupply generator ? powerdown mode ? pin compatible with mm74hc943 ? capable of driving 9 dbm into a 600 w load pin assignment p suffix plastic dip case 738 dw suffix sog package case 751d 20 1 20 1 v dd cdt cd lb dsi fb x in x out cda rxd 5 4 3 2 1 10 9 8 7 6 14 15 16 17 18 19 20 11 12 13 rxa1 txa exl v ag tla txd v ss mode sqt rxa2 ordering information mc145442p plastic dip MC145443P plastic dip mc145442dw sog package mc145443dw sog package rev 1 8/95 freescale semiconductor, inc.
mc145443 block diagram * refer to the fb pin description. 15 16 rxa2 rxa1 lb mode sqt txd tla x out x in 9 8 20 11 14 13 2 mode control modulator oscillator clock divider sampling clock: 77.82 khz sampling clock: 19.46 khz internal v ag analog ground generator 12 6 19 v ag aaf s/h lowband bpf highband bpf ac amp * smoothing filter 18 17 exi txa 1 10 dsi fb demod 5 rxd 3 carrier detect cd cda cdt 7 4 v dd v ss + + absolute maximum ratings (voltages referenced to v ss ) rating symbol value unit supply voltage v dd 0.5 to + 7.0 v dc input voltage v in 0.5 to v dd + 0.5 v dc output voltage v out 0.5 to v dd + 0.5 v clamp diode current, per pin i ik , i ok 20 ma dc output current, per pin i out 28 ma power dissipation p d 500 mw operating temperature range t a 40 to + 85 c storage temperature range t stg 65 to + 150 c recommended operating conditions parameter symbol min max unit supply voltage v dd 4.5 5.5 v dc input or output voltage v in , v out 0 v dd v input rise or fall time t r , t f e 500 ns crystal frequency* f crystal 3.2 5.0 mhz * changing the crystal frequency from 3.579 mhz will change the output frequencies. the change in output frequency will be proportional to the change in crystal frequency . this device contains circuitry to protect the inputs against damage due to high static volt - ages or electric fields; however , it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. for proper operation it is recommended that v in and v out be constrained to the range v ss (v in or v out ) v dd ). unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss or v dd ). freescale semiconductor, inc.
mc145442 3 dc electrical characteristics (v dd = 5.0 v 10%, t a = 40 to + 85 c) characteristic symbol min typ max unit highlevel input voltage lb x in , txd, mode, sqt v ih v dd 0.8 3.15 e e e e v lowlevel input voltage lb x in , txd, mode, sqt v il e e e e 0.8 1.1 v highlevel output voltage i oh = 20 m a cd , rxd i oh = 2 ma cd , rxd i oh = 20 m a x out v oh v dd 0.1 3.7 e e e v dd 0.05 e e e v lowlevel output voltage i ol = 20 m a cd , rxd i ol = 2 ma cd , rxd i ol = 20 m a x out v ol e e e e e 0.05 0.1 0.4 e v input current lb , txd, mode, sqt rxa1, rxa2 x in i in e e e e 10 e 1.0 12 10 m a quiesent supply current (x in or f crystal = 3.579 mhz) i dd e 7 10 ma powerdown supply current e 200 300 m a input capacitance x in all other inputs c in e e 10 e e 10 pf v ag output voltage (i o = 10 m a) v ag 2.4 2.5 2.6 v cda output voltage (i o = 10 m a) v cda 1.1 1.2 1.3 v line driver feedback resistor r f 10 20 30 k w ac electrical characteristics (v dd = 5.0 v 10%, t a = 40 to + 85 c, crystal frequency = 3.579 mhz 0.1%; see figure 1) characteristic min typ max unit transmitter power output on txa r l = 1.2 k w , r tla = r l = 1.2 k w , r tla = 5.5 k w 13 10 12 9 11 8 dbm second harmonic power r l = 1.2 k w e 56 e dbm receive filter and hybrid hybrid input impedance rxa1, rxa2 40 50 e k w fb output impedance e 16 e k w adjacent channel rejection 48 e e dbm demodulator receive carrier amplitude 48 e 12 dbm dynamic range e 36 e db bit jitter (s/n = 30 db, input = 38 dbm, bit rate = 300 baud) e 100 e m s bit bias e 5 e % carrier detect threshold on to off (cda = 1.2 v or cda grounded through a 0.1 m f capacitor) off to on e e 44 47 e e dbm freescale semiconductor, inc.
mc145443 test input 600 w 600 w v dd r tla 20 17 15 16 test output 4 cdt rxa1 c cdt c fb 0.1 m f 10 fb rxd 5 11 d out d in txd x in 9 8 x out tla txa rxa2 mc145442 mc145443 0.1 m f 3.579 mhz 0.1% figure 1. ac characteristics evaluation circuit pin descriptions v dd positive power supply (pin 6) this pin is normally tied to 5.0 v. v ss negative power supply (pin 12) this pin is normally tied to 0 v. v ag analog ground (pin 19) analog ground is internally biased to (v dd v ss ) / 2. this pin must be decoupled by a capacitor from v ag to v ss and a capacitor from v ag to v dd . analog ground is the common bias line used in the switched capacitor filters, limiter , and slicer in the demodulation circuitry. tla transmit level adjust (pin 20) this pin is used to adjust the transmit level. transmit level adjustment range is typically from 12 dbm to 9 dbm. (see applications information.) txd transmit data (pin 11) binary information is input to the transmit data pin. data entered for transmission is modulated using fsk techniques. a logic high input level represents a mark and a logic low rep - resents a space (see table 1). txa transmit carrier (pin 17) this is the output of the line driver amplifier . the transmit carrier is the digitally synthesized sine wave output of the modulator derived from a crystal oscillator reference. when a 3.579 mhz crystal is used the frequency outputs shown in table 1 apply. (see applications information .) table 1. bell 103 and ccitt v.21 frequency characteristics data originate mode answer mode data transmit receive transmit receive bell 103 (mc145443) space 1070 hz 2025 hz 2025 hz 1070 hz mark 1270 hz 2225 hz 2225 hz 1270 hz ccitt v.21 (mc145442) space 1180 hz 1850 hz 1850 hz 1180 hz mark 980 hz 1650 hz 1850 hz 980 hz note: actual frequencies may be ?? ?????? ???? ??? ?????? ?? ??? 15 db/octave 256 64 16 3.4 4 2 0 0 20 25 55 60 transmit carrier level (dbm) maximum level of outofband energy relative to the transmit carrier level into 600 w (khz) figure 2. outofband energy exi external input (pin 18) the e xterna l i nput i s t h e n oninvertin g i npu t t o t h e l ine driver. it is provided to combine an auxiliary audio signal or speech signal to the phone line using the line driver . this pin should be connected to v ag if not used. the average level must be the same as v ag to maintain proper operation. (see applications information .) dsi driver summing input (pin 1) the driver summing input may be used to connect an ex - ternal signal, such as a dtmf dialer , to the phone line. a series resistor , r dsi , is needed to define the voltage gain a v (see applications information and figure 6). when ap- plying a s igna l t o d o d s i p in , t h e m odulato r s houl d b e squelched by bringing sqt (pin 14) to a logic high level. the voltage gain, a v , is calculated by the formula a v = r f /r dsi (where r f ? ? w ). for example, a 20 k w resistor for r dsi will provide unity gain (a v = 20 k w /20 k w = 1). this pin must be left open if not used. rxd receive data (pin 6) the receive data output pin presents the digital binary data resulting from the demodulation of the receive carrier . if no carrier is present, cd high, the receive data output (rxd) is clamped high. freescale semiconductor, inc.
mc145442 5 rxa2, rxa1 receive carrier (pins 15, 16) the receive carrier is the fsk input to the demodulator through the receive bandpass filter . rxa1 is the noninvert - ing input and rxa2 is the inverting input of the receive hybrid (duplexer) operational amplifier. lb analog loopback (pin 2) when a high level is applied to this pin (sqt must be low), the analog loopback test is enabled. the analog loopback test connects the txa pin to the rxa2 pin and the rxa1 to analog g round. i n l oopback , t h e d emodulato r f requencies are switched to the modulation frequencies for the selected mode. (see tables 1 and 2 and figures 4c and 4d.) when lb is connected to analog ground (v ag ), the modu - lator g enerate s a n e ch o c ancellatio n t on e o f 2 10 0 h z f or mc145442 ccitt v .21 and 2225 hz for mc145443 bell 103 systems. for normal operation, this pin should be at a logic low level (v ss ). the powerdown mode is enabled when both lb and sqt are connected to a logic high level (see table 2). table 2. functional table mode pin 13 sqt pin 14 lb pin 2 operating mode 1 0 0 originate mode 0 0 0 answer mode x 0 v ag (v dd /2) echo tone x 0 1 analog loopback x 1 0 squelch mode x 1 v ag (v dd /2) squelch mode x 1 1 power down mode mode (pin 13) this i npu t s elect s t h e p ai r o f t ransmi t a n d f requencies used d urin g m odulatio n a n d d emodulation . w he n a l ogic high level is placed on this input, originate (bell) or channel 1 (ccitt) is selected. when a low level is placed on this input, answer ( bell ) o r c hanne l 2 ( ccitt ) i s s elected . ( see tables 1 and 2 and figure 4.) cdt carrier detect timing (pin 4) a capacitor on this pin to v ss sets the amount of time the carrier must be present before cd goes low (see applica- tions information for the capacitor values). cd carrier detect output (pin 3) this output is used to indicate when a carrier has been sensed by the carrier detect circuit. this output goes to a logi c l o w l eve l w he n a v alid s ignal a bov e t h e m aximum threshold level (defined by cda, pin 7) is maintained on the input to the hybrid circuit longer then the response (defined by cdt , pin 4). this pin is held at the logic low level until the signal f all s b elo w t h e m aximu m t hreshol d l eve l f o r l onger than the turn of f time. (see applications information and figure 5.) cda carrier detect adjust (pin 7) an external voltage may be applied to this pin to adjust the carrier detect threshold. the threshold hysteresis is internally fixed at 3 db (see applications information ). x out , x in crystal oscillator (pins 8, 9) a crystal reference oscillator is formed when a 3.579 mhz crystal is connected between these two pins. x out (pin 8) is the output of the oscillator circuit, and x in (pin 9) is the input to the oscillator circuit. when using an external clock, apply the clock to the x in (pin 9) pin and leave x out (pin 8) open. an internal 1 0 m w r esisto r a n d i nterna l c apacitors , t ypically 10 pf on x in and 16 pf on x out , allow the crystal to be con- nected without any other external components. printed cir - cuit board layout should keep external stray capacitance to a minimum. fb filter bias (pin 10) this is the negative input to the ac amplifier. in normal op- eration, t hi s p i n i s c onnecte d t o a nalo g g roun d t hroug h a 0.1 m f bypass capacitor in order to cancel the input of fset voltage of the limiter . it has a nominal input impedance of 16 k w . (see figure 3). sqt transmit squelch (pin 14) when this input pin is at a logic high level, the modulator is disabled. the line driver remains active if lb is at a logic low level (see table 2) . when b ot h l b a n d s q t a r e c onnecte d t o a l ogi c h igh level, see t able 2, the entire chip is in a power down state and all circuitry except the crystal oscillator is disabled. total power supply current decreases from 10 ma (max) to 300 m a (max). 0.1 m f fb 16 k w 10 490 k w + from bandpass filter to carrier detect circuit and demodulator figure 3. ac amplifier circuit freescale semiconductor, inc.
mc145443 general description the mc145442 and mc145443 are fullduplex lowspeed modems. they provide a 300baud fsk signal for bidirec - tional data transmission over the telephone network. they can be operated in one of four basic configurations as deter - mined by the state of mode (pin 13) and lb (pin 2). the normal ( nonloopback ) a n d s el f t es t ( loopback ) m odes i n both answer and originate modes will be discussed. for an originate or channel 1 mode, a logic high level is placed on mode (pin 13) and a logic low level is placed on lb (pin 2). in this mode, transmit data is input on txd, where it is converted to a fsk signal and routed through a low band bandpass filter. the filtered output signal is then buf f- ered by the tx opamp line driver , which is capable of driving 9 dbm onto a 600 w line. the receive signal is connected through a hybrid duplexer circuit on pins 15 and 16, rxa2 and rxa1. the signal then passes through the antialiasing filter, the sampleandhold circuit, is switched into the high band bandpass filter , and then switched into the ac amplifier circuit. the output of the ac amplifier circuit is routed to the demodulator circuit and demodulated. the resulting digital data is then output through rxd (pin 5). the carrier detect circuit receives its signal from the output of the ac amplifier circuit and goes low when the incoming signal is detected (see figure 4a). in t h e a nswe r o r c hanne l 2 m ode , a l ogi c l o w l eve l i s placed on mode (pin 13) and on lb (pin 2). in this mode, the d at a f ollow s t h e s am e p ath e xcep t t h e f s k s igna l i s routed to the highband bandpass filter and the sample andhold signal is routed through the lowband bandpass filter. (see figure 4b.) in the analog loopback originate or channel 1 mode, a logic high level is placed on mode (pin 13) and on lb (pin 2). this mode is used for a self check of the modulator , demodu - lator, and lowband passband filter circuit. the modulator side is configured exactly like the originate mode above ex - cept the line driver output (txa, pin 17) is switched to the negative input of the hybrid opamp. the rxa2 input pin is open in this mode and the noninverting input of the hybrid circuit is connected to v ag . the sampleandhold output by - passes the filter so that the demodulator receives the modu- lated tx data (see figure 4c). this test checks all internal device components except the highband bandpass filter , which can be checked in the answer or channel 2 mode test. in the analog loopback or channel 2 mode, a logic low level is placed on mode (pin 13) and a logic high level on lb (pin 2). this mode is used for a self check of the modulator, demodulator, a n d h ighban d p assband f ilte r c ircuit . t his configuration i s e xactl y l ik e t he o riginat e l oopbac k m ode above, except the signal is routed through the highband passband filter (see figure 4d). freescale semiconductor, inc.
mc145442 7 15 16 11 rxa2 rxa1 txd + aaf s/h modulator lowband bpf highband bpf ac amp smoothing filter carrier detect demod + 3 5 1 17 18 cd rxd dsi txa exl (a) originate/channel 1 mode (mode = high, lb = low) (b) answer/channel 2 mode (mode = low, lb = low) 15 16 11 rxa2 rxa1 txd + aaf s/h modulator lowband bpf highband bpf ac amp smoothing filter carrier detect demod + 3 5 1 17 18 cd rxd dsi txa exl 15 16 11 rxa2 rxa1 txd + aaf s/h modulator lowband bpf highband bpf ac amp smoothing filter carrier detect demod + 3 5 1 17 18 cd rxd dsi txa exl (c) originate/channel 1 mode and analog loopback state (mode = high, lb = low) + aaf s/h modulator lowband bpf highband bpf ac amp smoothing filter carrier detect demod + 3 5 1 17 18 cd rxd dsi txa exl 15 16 11 rxa2 rxa1 txd (d) answer/channel 2 mode and analog loopback state (mode = low, lb = low) figure 4. basic operating modes freescale semiconductor, inc.
mc145443 applications information carrier detect timing adjustment the value of a capacitor , c cdt at cdt (pin 4) determines how long a received modem signal must be present above the minimum threshold level before cd (pin 3) goes low . the c cdt capacitor also determines how long the cd pin stays low after the received modem signal goes below the mini - mum threshold. the cd pin is used to distinguish a strong modem signal from random noise. the following equations show the relationship between t cdl , the time in seconds re- quired for cd to go low; t cdh , the time in seconds required for cd to go high; and c cdt , the capacitor value in m f. valid signal to cd response time: t cdl 6.4 c cdt invalid signal to cd off time: t cdh 0.54 c cdt example: t cdl 6.4 0.1 m f 0.64 seconds t cdh 0.54 0.1 m f 0.054 seconds carrier detect threshold adjustment the carrier detect threshold is set by internal resistors to activate cd with a typical 44 dbm (into 600 w ) signal and deactivate cd with a typical 47 dbm signal applied to the input of the hybrid circuit. the carrier detect threshold level can b e a djuste d b y a pplyin g a n e xterna l v oltag e o n c da (pin 7). the following equations may be used to find the cda voltage required for a given threshold voltage. (v on and v off are in vrms.) v cda = 244 v on v cda = 345 v off example (internally set) v on = 4.9 mv 44 dbm: v cda = 244 4.9 mv = 1.2 v v off = 3.5 mv 47 dbm: v cda = 345 3.5 mv = 1.2 v example (externally set) v on = 7.7 mv 40 dbm: v cda = 244 7.7 mv = 1.9 v v off = 5.4 mv 43 dbm: v cda = 345 5.4 mv = 1.9 v the c d a p in h a s a n a pproximat e t heveni n e quivalent voltage of 1.2 v and an output impedance of 100 k w . when using the internal 1.2 v reference a 0.1 m f capacitor should be connected between this pin and v ss (see figure 5). transmit level adjustment the power output at txa (pin 17) is determined by the value of resistor r tla that is connected between tla (pin 20) to v dd (pin 6). t able 3 shows the r tla values and the corresponding power output for a 600 w load. the voltage at txa is twice the value of that at ring and tip because txa feeds the signal through a 600 w resistor r tx to a 600 w line transformer (see figure 7). when choosing resistor r tla , keep in mind that 9 dbm is the maximum output level al - lowed from a modem onto the telephone line (in the u.s.). in addition, keep in mind that maximizing the power output from the modem optimizes the signaltonoise ratio, improving accurate data transmission. table 3. transmit level adjust output transmit level (typical into 600 w ) r tla 12 dbm 11 dbm 19.8 k w 10 dbm 9.2 k w 9 dbm 5.5 k w the line driver the line driver is a power amplifier used for driving the telephone line. both the inverting and noninverting input to the line driver are available for transmitting externally gener- ated tones. exl (pin 18) is the noninverting input to the line driver and gives a fixed gain of 2 (r i = 50 k w ). the average signal level must be the same as v ag to maintain proper operation. this pin should be connected to v ag if not used. the driver summing input (dsi, pin 1) may be used to con - nect an external signal, such as a dtmf dialer , to the phone line. when applying a signal to the dsi pin, the modulator should be squelched by bringing sqt (pin 14) to a logic high level. dsi must be left open if not used. in addition, the dsi pin is the inverting side of the line driv - er and allows adjustable gain with a series resistor r dsi (see figure 6 ) . t h e v oltag e g ain , a v , i s d etermine d b y t he equation: a v = r f r dsi where r f 20 k w. example: a resistor value of 20 k w for rdsi will provide unity gain. a v = (20 k w /20 k w ) = 1 freescale semiconductor, inc.
mc145442 9 hybrid ac amp autonulled comparator 6 ms retriggerable oneshot 3 cd 4 cdt sampling clock threshold control v cda 1.2 v 7 16 rxa1 cda c cda 0.1 m f c cdt 0.1 m f v ref v dd figure 5. carrier detect circuit modulator output r 0 = r f r 0 r f r i v ag 19 exi 18 dsi 1 txa 17 + r dsi figure 6. line driver using the dsi input freescale semiconductor, inc.
mc145443 20 6 9 19 10 1 17 15 16 dtmf input 20 k w r tx 600 w + 10 w tip ring * 0.1 m f 4 19 10 18 cdt v ag fb exl rxa1 txa rxa2 dsi tla v dd mc145442/3 gnd cda mode lb sqt rxd txd cd x in x out 8 7 12 3.58 mhz 11 15 13 8 2 3 7 6 8 7 9 2 4 + 5 v rx3 rx2 tx1 rx1 tx2 gnd stby txen di1 di2 do1 v cc mc145407 eia232d db25 connector 0.1 m f v dd 10 m f 0.1 m f 0.1 m f c cdt 0.1 m f c fb r dsi c dsi r tla c cda 0.1 m f 10 k w v dd v ss 10 k w 10 k w 0.1 m f 0.1 m f 20 c1+ c1 18 c1+ c1 1 3 0.1 m f 17 mmbz15vdlt1 x 3 * line protection circuit figure 7. typical mc145442/mc145443 applications circuit freescale semiconductor, inc.
mc145442 11 package dimensions p suffix plastic dip case 73803 1.070 0.260 0.180 0.022 0.070 0.015 0.140 15 0.040 1.010 0.240 0.150 0.015 0.050 0.008 0.110 0 0.020 25.66 6.10 3.81 0.39 1.27 0.21 2.80 0 0.51 27.17 6.60 4.57 0.55 1.77 0.38 3.55 15 1.01 0.050 bsc 0.100 bsc 0.300 bsc 1.27 bsc 2.54 bsc 7.62 bsc min min max max inches millimeters dim a b c d e f g j k l m n notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimension b does not include mold flash. -a- c k n e g f d 20 pl j 20 pl l m -t- seating plane 1 10 11 20 0.25 (0.010) t a m m 0.25 (0.010) t b m m b dw suffix sog package case 751d04 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.150 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.13 (0.005) total in excess of d dimension at maximum material condition. a b 20 1 11 10 s a m 0.010 (0.25) b s t d 20x m b m 0.010 (0.25) p 10x j f g 18x k c t seating plane m r x 45 dim min max min max inches millimeters a 12.65 12.95 0.499 0.510 b 7.40 7.60 0.292 0.299 c 2.35 2.65 0.093 0.104 d 0.35 0.49 0.014 0.019 f 0.50 0.90 0.020 0.035 g 1.27 bsc 0.050 bsc j 0.25 0.32 0.010 0.012 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 10.05 10.55 0.395 0.415 r 0.25 0.75 0.010 0.029 freescale semiconductor, inc.
mc145443 ? freescale semiconductor, inc.

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